Projects

Joint work by SLAC and ELTE presents a fully pipelined detector-to-LPU framework on the Groq GC1 card: a direct QSFP link connects non-deterministic detector inputs to deterministic LPU compute. The demonstration brings DIII-D CAKE-NN inference to about 10 μs end-to-end latency, with an FPGA-based controller between detector systems and the LPU that mediates timing and data flow.

A high-performance quantum gate decomposer and compiler for optimizing quantum circuits. SQUANDER provides efficient algorithms for decomposing arbitrary quantum gates into native gate sets and optimizing quantum circuit implementations.

A photonic quantum computing simulator for continuous-variable quantum computation. Piquasso enables simulation of quantum optical systems, boson sampling, and Gaussian state quantum computing with both Fock and Gaussian state representations.

This work introduces a novel optimization approach designed to alleviate the adverse effects of barren plateaus (BP) during variational quantum circuit training. In contrast to conventional gradient descent methods, our approach relies on making finite hops along search directions determined on randomly chosen subsets of free parameters. The optimization search direction and range are determined by distant features of the cost-function landscape, enabling navigation around barren plateaus without external control mechanisms. Successfully applied to quantum circuits comprising 21 qubits and 15,000 entangling gates, demonstrating robust resistance against BPs.

This work generalizes the Balasubramanian–Bax–Franklin–Glynn permanent formula to efficiently integrate it into boson sampling strategies. By incorporating n-ary Gray code ordering of addends during permanent evaluation, we achieve a reduction in simulation complexity. Implementing the algorithm on FPGA-based data-flow engines enables acceleration of boson sampling simulations for up to 40 photons, drawing samples from a 60-mode interferometer at an average rate of 80 seconds per sample using 4 FPGA chips.

This work demonstrates the use of Field Programmable Gate Array (FPGA) based data-flow engines (DFEs) to scale up variational quantum compilers for synthesizing circuits up to 9-qubit programs. The gate decomposer utilizes a newly developed DFE quantum computer simulator designed to simulate arbitrary quantum circuits consisting of single qubit rotations and controlled two-qubit gates on FPGA chips.

Eötvös Quantum Transport Utilities (EQuUs) - A collection of computational tools for theoretical investigation of quantum transport phenomena in solid state systems. The utilities support research on mesoscopic systems, carbon-based materials, and quantum transport properties.